In the recent years, a universal measurement setup for high-resolution ADC testing at the frequency band of 0.5 - 20 MHz was designed and prototyped at the Czech Technical University. Parameters of harmonic signal are analysed in contribution, which is needed for inverters testing and further a construction of a special generator with high spectral purity is described.

A D/A subconverter (DASC) error correction scheme based on weighting capacitor rotation is adapted to account for finite op-amp gain. Simulations show that reasonable estimates of capacitor mismatch can be obtained even if the actual gain is replaced by a nominal gain differing by as much as a factor of two.
DASC capacitor mismatch might therefore be estimated in the foreground at power-up, and most part of the correspondingmismatch noise and mismatch-induced interstage gain error might be cancelled, possibly delegating to a background calibration the task of correcting the remaining interstage gain error, induced by finite op-amp gain and drift with temperature.

This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling both the unit load capacitors and the discharge current of the load capacitance using current DAC. The proposed CTDSA achieves 610 fs resolution and ~2.5 ns dynamic range. The total simulated power consumption is 25.8 mW with 5 MHz conversion rate with 3 V supply. The design was simulated using a 0.35 µm CMOS process.

We present a time-to-digital converter with a virtual time coding line created as an equivalent of two independent time coding lines operating simultaneously. Proposed solution allows to overcome the technology limitation in achievable resolution and improve the precision of conversion. The new coding line used in the interpolating time counter designed in an FPGA CMOS device provides the precision (standard deviation) below 35 ps within a 1 s measurement range.

A diagnostic system being designed to measure the beam phase and energy of the Drift Tube Linac (DTL) in the Proton Accelerator of China Spallation Neutron Source (CSNS) is described and the characterization of the prototype is presented. The signals received from Fast Current Transformers (FCTs) are Radio Frequency (RF) signals with the frequency up to 350 MHz and a dynamic range of -30 dBm to 3.5 dBm. The RF signals are converted to orthogonal streams directly with the In-phase and Quadrature-phase (IQ) undersampling technique based on high-speed high-resolution A/D conversion. Thus a high quality sampling clock system is indispensable. Two different clock systems are implemented and tested for comparison. All Digital Signal Processing (DSP) algorithms are implemented in one single FPGA, meanwhile a Nios II embedded system is also integrated in it for data transfer through the Ethernet. This system achieves a phase resolution better than 0.07 degree over the input signal amplitude range of -41 dBm to 7 dBm.