TIME-TO-DIGITAL CONVERTER (TDC) WITH SUB-PS-LEVEL RESOLUTION USING CURRENT DAC AND DIGITALLY CONTROLLABLE LOAD CAPACITOR |
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| Salim Alahdab, AnttiMantyniemi, Juha Kostamovaara |
- Abstract:
- This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling both the unit load capacitors and the discharge current of the load capacitance using current DAC. The proposed CTDSA achieves 610 fs resolution and ~2.5 ns dynamic range. The total simulated power consumption is 25.8 mW with 5 MHz conversion rate with 3 V supply. The design was simulated using a 0.35 µm CMOS process.
- Download:
- IMEKO-IWADC-2011-14.pdf
- DOI:
- -
- Event details
- IMEKO TC:
- TC4
- Event name:
- IWADC 2011
- Title:
16th IMEKO International Workshop on ADC Modeling and Testing - Data Converter Design, Modeling and Testing (together with IEEE ADC Forum) (IWADC)
- Place:
- Orvieto, ITALY
- Time:
- 30 June 2011 - 01 July 2011