High frequency & resolution ADC: Trends and Modeling
Richard Morisson
Abstract:
The analog to digital converter is one of the key devices for future receiver design taking into account performance and cost. Is this dream for true software radio applications ( within certain conditions) achievable in a few years ? Developing such application will mean very high analog input intermediate frequency with wide bandwidth to be converted with very low spurious intermodulation (much better than – 85 db) translating to 12..14 bit resolution ADC sampled at very high clock rates. Modeling of such a specification gives special restriction on the choice of the ADC architecture and process. It can be proven that the only architecture suitable for this future radio application is a massive parallel structure. Introducing such a high linearity ADC without any feedback loop needs new parallel DC and AC linearisation in the analog core to correct mismatching. The choice of the process to use is an other key: CMOS, Bipolar, BiCmos processes have been studied. Taking into account high frequency clock and analog inputs, high resolution, low noise and low power, only BCMOS of Bipolar (with Vpnp) featuring a high Ft and good matching of components are good candidates. Several ADC have been realized or simulated : starting from 10 bits 1 Gsps or 2 Gsps to 14 bits 200 MSPS with Bicmos or Bipolar process with an Ft of 25 or 75 GHz (SiGe).
Keywords:
Software radio, Digital receiver, Pipeline ADC, Flash ADC, Folding and interpolation ADC, Dithering
