ANALYSIS OF A MULTIPLYING DAC EMPLOYED FOR SYNCHRONOUS DETECTION
Umberto Pogliano
Abstract:
Multiplying digital to analog converters can be used as synchronous detection circuits by combining a proper code sequence and an analog input at the reference. The output for a periodic signal has been derived under reasonable assumptions. The analysis shows that this type of synchronous detector is sensible only to harmonic components almost equal to a multiple of the number of samples per period. This result can be seen as a generalization of the classical two-level synchronous detection theory.
Download:
IMEKO-IWADC-2004-008.pdf
DOI:
-
Event details
IMEKO TC:
TC4
Event name:
IWADC 2004
Title:

IXth International Workshop on ADC Modeling and Testing, IWADC (together with XIII IMEKO TC4 International Symposium on Measurements for Research and Industrial Applications) (IWADC)

Place:
Athens, GREECE
Time:
29 September 2004 - 01 October 2004
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