OPTIMIZED DECIMATION STRUCTURE FOR COMPLEX BANDPASS ΣΔ MODULATOR IN WIDEBAND RECEIVER |
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| Haifa FARES, Chiheb REBAI, Bertrand LE GAL, Dominique DALLET |
- Abstract:
- This paper presents an efficient design of a decimation filter for a continuous-time (CT) complex bandpass ΔΣ modulator in wideband-standards receiver. The RF front-end has been based on a modified low-IF architecture and the full receiver dynamic range is converted into the digital domain. The approach proposed investigates a new decimation process and realizes new functionalities such as image rejection and frequency down conversion IF/DC by a complex mixing on ΣΔ modulator bit stream. Two wide standards (IEEE 802.11a and 802.16) were chosen for design procedure illustration. The decimation structure was implemented on FPGA component using optimization techniques. Experimental results show the highspeed data rate and low-power consumption features of the proposed design.
- Download:
- IMEKO-IWADC-2008-095.pdf
- DOI:
- -
- Event details
- IMEKO TC:
- TC4
- Event name:
- IWADC 2008
- Title:
13th IMEKO TC4 Workshop on ADC Modelling and Testing IWADC (together with XVIth IMEKO TC4 International Symposium on Electrical Measurements and Instrumentation) (IWADC)
- Place:
- Florence, ITALY
- Time:
- 22 September 2008 - 24 September 2008